English for Verilog and VHDL Developers

Hardware description languages look like software languages but describe physical circuits, and that gap is exactly where miscommunication happens most: a line of Verilog doesn’t execute — it describes hardware that exists all at once, and the vocabulary needs to reflect that difference precisely.

Key Vocabulary

RTL (register-transfer level) — the abstraction level at which most Verilog and VHDL design happens, describing how data moves between registers on each clock cycle and what combinational logic sits between them, rather than a literal gate-level or transistor-level description. “We’re reviewing this at the RTL level, so focus on whether the data actually reaches the right register on the right clock edge — gate-level timing details are the synthesis tool’s problem at this stage, not ours.”

Synthesis — the automated process of converting RTL code into an actual gate-level netlist targeting a specific technology (an FPGA or ASIC library), during which code that behaves identically in simulation can synthesize into very different, or even non-functional, hardware. “This simulates correctly, but it won’t synthesize the way you’d expect — that construct isn’t synthesizable on this target, so the synthesis tool will either reject it outright or infer hardware very different from what you simulated.”

Blocking vs. non-blocking assignment — Verilog’s two assignment operators (= for blocking, <= for non-blocking), where blocking assignments execute and complete sequentially within a block while non-blocking assignments all schedule to update simultaneously at the end of the current time step, a distinction that changes actual synthesized behavior, not just style. “Swap that blocking assignment for a non-blocking one inside the clocked always block — with blocking assignment here, this register update depends on evaluation order in a way that doesn’t match the flip-flop behavior you’re actually trying to model.”

Timing closure — the point at which a synthesized and placed-and-routed design meets all its timing constraints (setup and hold times) across every path, at every corner, achieved through iterative optimization rather than guaranteed by simply writing correct RTL. “Functionally correct RTL doesn’t mean we’re done — we still haven’t hit timing closure on the critical path between the multiplier output and the accumulator register, so we need to either pipeline that path or relax the clock frequency.”

Testbench — a non-synthesizable simulation environment written to drive stimulus into a design under test and check its outputs, distinct from the RTL design itself, since a testbench can use constructs (like delays or file I/O) that could never become real hardware. “Don’t worry that this uses a #10 delay and file reads — none of that needs to be synthesizable, since it’s testbench code exercising the design under test, not part of the design itself.”

Common Phrases

• “Are we reviewing this at the RTL level, or does the gate-level detail actually matter here?”
• “Does this construct actually synthesize, or does it only work in simulation?”
• “Is that a blocking or non-blocking assignment, and does it match the behavior we’re trying to model?”
• “Have we hit timing closure on this path, or is it still failing at the target clock frequency?”
• “Is that testbench code, or does it need to be synthesizable?”

Example Sentences

Explaining a synthesis mismatch: “The simulation passed because the simulator evaluates this loop the way you’d expect from software, but it’s not synthesizable as written — the synthesis tool can’t infer bounded hardware from an unbounded loop condition like this.”

Flagging an assignment bug in review: “This clocked block mixes blocking and non-blocking assignments to the same signal, which is a classic source of simulation-versus-synthesis mismatch — standardize on non-blocking assignments throughout this always block.”

Reporting timing status: “RTL is functionally verified and matches the spec, but we’re not done — the path from the DMA controller to the output FIFO is still 400 picoseconds short of timing closure at the target frequency, so it needs another pipeline stage.”

Professional Tips

• Communicate explicitly which abstraction you’re discussing — RTL behavior, gate-level netlist, or physical layout — since a bug reported at the wrong level sends the wrong engineer chasing the wrong problem.
• Never assume simulation correctness implies synthesis correctness — always confirm a construct is synthesizable on the actual target before relying on simulated behavior, especially for anything unusual like loops with variable bounds.
• Standardize on non-blocking assignment for all clocked sequential logic and blocking assignment for combinational logic — mixing the two within the same always block is one of the most common sources of subtle simulation-versus-hardware mismatches.
• Report timing closure status as its own explicit milestone, separate from functional verification — a design can be functionally perfect in simulation and still fail in real hardware if it doesn’t meet timing at the target clock frequency.
• Keep testbench code and design code clearly separated in both files and conversation — testbench constructs that aren’t synthesizable are completely normal and expected, but only inside the testbench, never inside the design under test.

Practice Exercise

1. Explain the difference between RTL and gate-level abstraction in hardware design.
2. Describe why blocking and non-blocking assignments can produce different synthesized behavior even when simulation results look identical.
3. Write a sentence explaining why timing closure is reported separately from functional correctness.

Navigating the Nuances of Feedback

As a Verilog or VHDL developer, you’re not just writing code; you’re crafting specifications that will be scrutinized by others – reviewers, synthesizers, and ultimately, your team. The quality of feedback you receive (and give) directly impacts the efficiency of the design process and the final product’s performance. Often, native English speakers struggle with the precise language used to describe these technical aspects, leading to misunderstandings and rework. Let’s focus on refining how you communicate about key concepts like synthesis versus simulation, blocking vs. non-blocking assignments, and even the somewhat nebulous world of timing closure.

One common area for confusion is distinguishing between simulation and synthesis. Saying “it doesn’t simulate correctly” isn’t helpful to a synthesizer; it needs to understand why it’s not simulating correctly – perhaps due to incorrect logic representation or an inadequate testbench. Similarly, stating “I used blocking assignments” might be met with a question of “Why? Blocking assignments can lead to unpredictable timing and are generally discouraged in modern RTL design.” Framing feedback as “The simulation results indicate a potential race condition that needs investigation” or “The synthesis tool is producing an unnecessarily large gate count due to the use of blocking logic. Consider transitioning to non-blocking for improved timing and predictability” is far more actionable. The goal is always clarity, focusing on what needs fixing rather than simply stating that it’s wrong.

Another frequently encountered challenge comes with explaining the subtleties of blocking vs. non-blocking assignments. Describing a non-blocking assignment as “not interfering” can be misleading. It’s more accurate to say it “doesn’t directly drive the output signal in the next time step,” allowing for proper concurrent behavior and minimizing potential timing issues. Conversely, stating that a blocking assignment is “fast” isn’t necessarily beneficial – its speed comes with increased complexity and the risk of introducing timing problems if not carefully managed. Using precise terminology like “synchronous” versus “asynchronous” when discussing concurrency becomes crucial.

Finally, remember that discussions around timing closure are often steeped in technical jargon. Phrases like “meeting the clock edge” or “optimizing for worst-case paths” can be confusing without a clear understanding of how these concepts relate to synthesis and simulation. Focusing on concrete metrics – cycle counts, path delays – and articulating the reason for any timing adjustments is paramount.

Here’s an example of how you might use vhlsynth to demonstrate the impact of different logic styles:

vhlsynth -property integer delay = 2 -property clocking = synchronous my_module.v

This command, using vhlsynth, attempts to synthesize a module named my_module.v. The -property integer delay = 2 specifies an integer delay of 2 units (a placeholder for actual timing), while -property clocking = synchronous indicates the use of synchronous logic. This simple command highlights how seemingly minor choices – like specifying synchronous versus asynchronous behavior – can dramatically affect the synthesis process and, ultimately, the final design’s performance.