Practise vocabulary for Makefile targets, prerequisites, task runners, and build automation communication.
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In a Makefile, a '.PHONY' target declaration is used for:
.PHONY prevents Make from treating target names like 'clean', 'build', 'test' as file names. Without .PHONY, if a file named 'clean' existed, 'make clean' would do nothing. .PHONY ensures the recipe always runs.
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In a Makefile, the phrase 'Run `make install` to install dependencies, then `make build` to compile the project' indicates:
If build does not list install as a prerequisite, Make won't run install automatically. The README sequence documents the manual workflow. Better practice: make install a prerequisite of build so 'make build' automatically runs 'make install' if needed.
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Task runner alternatives like 'just' and 'taskfile' are described as being different from Make in that they:
Make was designed for C compilation dependency management. Using Make purely as a task runner works but can be confusing: .PHONY requirements, tab-only indentation, complex variable expansion. 'just' and 'Taskfile' are purpose-built task runners without the file-dependency complexity.
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Automatic variables in a Makefile like '$@' and '$<' represent:
Automatic variables enable pattern rules: '%: %.c' with recipe '$(CC) -o $@ $<' compiles any .c file. $@ = current target, $< = first prerequisite (the .c file), $^ = all prerequisites. Without these, you'd need separate rules for every file.
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The `$(MAKE)` variable should be used instead of `make` inside a Makefile recipe because:
Using $(MAKE) for recursive calls ensures flag consistency: if the user runs 'make -j8', sub-makes also run with -j8. Using bare 'make' would lose flags and might use a different Make binary on systems with multiple versions installed.