5 exercises on interrupt-driven firmware terminology: interrupt, ISR, interrupt latency, critical section, and atomic operation. Advanced
0 / 5 completed
1 / 5
An engineer says: "The UART fired an interrupt as soon as a byte arrived."
What is an interrupt in embedded systems?
Correct: B. An interrupt is an asynchronous event mechanism. When a peripheral (UART, timer, GPIO, etc.) needs CPU attention, it asserts an interrupt line. The CPU finishes its current instruction, saves its state, and jumps to the interrupt handler. This is far more efficient than polling.
Type
Source
Example
Hardware interrupt
Peripheral signals CPU
UART RX, timer overflow, GPIO edge
Software interrupt
Instruction triggers handler
SVC (system call) on ARM Cortex-M
Exception / fault
CPU detects error condition
HardFault, MemManage on ARM
2 / 5
During a code review your lead comments: "Keep your ISR as short as possible — just set a flag and defer all processing to a task."
What is an ISR?
Correct: B. An ISR (Interrupt Service Routine) is the C function (or assembly routine) that executes when an interrupt fires. Because ISRs run with the normal task scheduler suspended or at elevated priority, keeping them brief is critical. The recommended pattern is to set a flag or post to a queue in the ISR, then process the data in a regular task.
Rule
Reason
No blocking calls
ISR cannot wait; it would hang the system
Minimal work
Keeps interrupt latency low for other interrupts
ISR-safe RTOS calls
Use xQueueSendFromISR(), not xQueueSend()
3 / 5
A spec requirement states: "The system must achieve an interrupt latency of less than 5 µs for the safety shutdown interrupt."
What is interrupt latency?
Correct: B.Interrupt latency is the end-to-end delay from interrupt assertion to ISR entry. It is a critical real-time metric. Sources of latency include: CPU pipeline flush cycles, interrupt controller arbitration, and — most significantly in RTOS systems — critical sections that temporarily disable interrupts.
Latency component
Description
Hardware latency
CPU pipeline + interrupt controller cycles
Software latency
Time interrupts are disabled in critical sections
Interrupt response time
Latency + time to finish current ISR if nested
4 / 5
A senior engineer instructs you: "Wrap that GPIO read-modify-write sequence in a critical section — it's not safe to be interrupted mid-operation."
What is a critical section?
Correct: B. A critical section guards shared data from race conditions. In bare-metal code this usually means disabling all interrupts for the duration. In RTOS code it may mean disabling the scheduler (taskENTER_CRITICAL()) or acquiring a mutex. Critical sections must be as short as possible to minimize interrupt latency impact.
Implementation
Trade-off
Disable all interrupts
Simplest; increases interrupt latency
RTOS scheduler lock
Allows ISRs; prevents task preemption only
Mutex
Per-resource; caller may block if already held
5 / 5
Your team's coding standard states: "Use an atomic read-modify-write instruction to update the status flag shared between the ISR and the main task."
What makes an operation atomic?
Correct: B. An atomic operation is one that, from the perspective of all other concurrent actors, either has not started or has fully completed — there is no observable intermediate state. On ARM Cortex-M this is achieved with exclusive load/store instructions (LDREX/STREX) or single-width volatile reads/writes on naturally aligned data, or via compiler intrinsics like __atomic_fetch_or().